Files
colibri-strix/c
Dog279 8040dac645 IDOT: AVX-512 VNNI kernel paths + batch-size gate for single-row int4 (+20% decode on Xeon) (#9)
- dot_i8i8/dot_i4i8: guarded __AVX512VNNI__ branches using vpdpbusd
  (64 bytes/iter, s32 accumulation, no 16-bit intermediate). AVX-512 has
  no vpsignb, so the sign trick becomes abs(w) + mask-negate on x.
- dot_i4i8: nibble unpack stays 256-bit; activation blocks are permuted
  to match the per-lane value order instead of re-sorting weights.
- The int4 IDOT gate (was hardcoded S>=2, from AVX2 measurements) becomes
  g_i4s with a VNNI-aware default of 1: single-row decode goes through the
  integer path where it now pays. I4S=n overrides for A/B; I4S=2 restores
  the old behavior exactly. AVX2/NEON/scalar builds are unchanged.
- Startup banner reports the active idot kernel (avx512-vnni/avx2/neon/scalar).

Measured on Xeon 6 (24C, AVX512-VNNI), DDR5-5600, ~19.8 GB/s NVMe RAID0,
gcc 13.3 -march=native: 256-tok greedy decode 1.72 -> 2.08 tok/s (+21%),
expert-matmul -24%; second prompt +20%. Integer-path outputs bit-identical
(associative s32 adds, same no-saturation bounds); S=1 int4 adopts the same
int8-activation tradeoff IDOT already makes for S>=2.

Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
2026-07-09 12:44:40 +02:00
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